New

FSM Global Yield FEOL (Front-End-Of-Line) Process Integration Development Engineer/6 months ago

Hsinchu, Taiwan

intel.com

Monthly Salary: $15,150 - $20,204

Application ends: Oct 01, 2024

Overview:

This job requisition is to seek FEOL (Front-End-Of-Line) Process Integration Development engineering roles in the FSM HVM Global Yield organization, reporting to the FEOL Process Integration Engineering Development manager. Selected candidates will work with other members in FEOL integration, other teams in Global Yield org, fab module, yield, and TD team members to achieve yield ramp-up and process optimization in the early production stage, supporting internal and external customers. FEOL (Front-End-Of-Line) Integration Development engineers responsibilities include (but are not limited to) Own engineering projects to execute HVM yield roadmap, device targeting, and attain performance targets. Collaborate with Technology Development and Local Yield teams to import new technology to production fabs. Work with FEOL/BEOL Integration, Device, Defect Reduction, and Yield Analysis team members to identify the root cause of yield/performance issues and implement a mitigation plan in the defined timeline to meet committed production yield/performance targets and to support fast-paced yield ramp-up in high-volume manufacturing phases.

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